POLISH ACADEMY of SCIENCES
TECHNICAL SCIENCES
| BULLETIN
of the
POLISH ACADEMY of SCIENCES TECHNICAL SCIENCES |
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| Volume
58, Issue 1, March 2010
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files | mirror: http://fluid.ippt.gov.pl/~bulletin/ |
| pp 125 - 128 |
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Power equalization of AES FPGA implementation |
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| M. STRACHACKI and S. SZCZEPANSKI |
| This paper briefly introduces side channel attacks on cryptographic hardware with special emphasis on differential power analysis (DPA). Based on existing countermeasures against DPA, design method combining power equalization for synchronous and combinatorial circuits has been proposed. AES algorithm has been implemented in Xilinx Spartan IIE field programmable gate array (FPGA) device using the standard and powerequalized methods. Power traces for DPA have been collected using XPower tool. Simulation results show that standard AES implementation can be broken after N=500 encryptions, while powerequalized counterpart shows no correlation between power consumption and the cipher key after N=2000 encryptions. |
| Key words: |
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AES, FPGA, cryptography, side channel attack, DPA, power analysis, power equalization |
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files |
| Copyright ® Bulletin of the Polish Academy of Sciences: Technical Sciences |
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