POLISH ACADEMY of SCIENCES
TECHNICAL SCIENCES
| BULLETIN
of the
POLISH ACADEMY of SCIENCES TECHNICAL SCIENCES |
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| Volume
58, Issue 1, March 2010
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| Issue Index | Authors Index | Scope Index | Web Info | |
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files | mirror: http://fluid.ippt.gov.pl/~bulletin/ |
| pp 119 - 124 |
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Heat dissipation and temperature distribution in long interconnect lines |
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| K. GNIDZINSKA , G. DE MEY , and A. NAPIERALSKI |
| Thermal and time delay aspects of long interconnect lines have been investigated. To design a modern integrated circuit we need to focus on very long global interconnects in order to achieve the desired frequency and signal synchronization. The long interconnection lines introduce significant time delays and heat generation in the driver transistors. Introducing buffers helps to spread the heat production more homogenously along the line but consumes extra power and chip area. To ensure the functionality of the circuit, it is compulsory to give priority to the time delay aspect and then the optimized solution is found by making the power dissipation as homogenous as possible and consequently the temperature distribution T (relative to ambient) as low as possible. The technology used for simulations is 65 nm node. The occurring phenomena have been described in a quantitative and qualitative way. |
| Key words: |
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interconnect lines, heat dissipation, delay, temperature distribution |
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| Issue Index | Authors Index | Scope Index | Web Info |
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files |
| Copyright ® Bulletin of the Polish Academy of Sciences: Technical Sciences |
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