POLISH ACADEMY of SCIENCES
TECHNICAL SCIENCES
| BULLETIN
of the
POLISH ACADEMY of SCIENCES TECHNICAL SCIENCES |
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| Volume
59, Issue 2, June 2011
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files | mirror: http://fluid.ippt.gov.pl/~bulletin/ |
| pp 141 - 147 |
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CMOS realisation of analogue processor for early vision processing |
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| W. JENDERNALIK, J. JAKUSZ, G. BLAKIEWICZ, R. PIOTROWSKI, and S. SZCZEPANSKI |
| The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated using a 0.35 µm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several µW. Finally, the experimental results are presented and discussed. |
| Key words: |
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CMOS imager, analogue processor array, smart sensor, vision chip |
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| Issue Index | Authors Index | Scope Index | Web Info |
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files |
| Copyright ® Bulletin of the Polish Academy of Sciences: Technical Sciences |
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