BULLETIN of the

POLISH ACADEMY of SCIENCES

TECHNICAL SCIENCES

BULLETIN of the POLISH ACADEMY of SCIENCES: TECHNICAL SCIENCES
Volume 56, Issue 3, September 2008

Electronics

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pp 229 - 238

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On reducing PLC response time

M. CHMIEL
The dual core bit-byte CPU must be equipped with properly designed circuits, providing interface between the two processor units, and making it possible to exploit all its advantages like versatility of the byte unit and speed of the bit unit. First of all, the interface circuits should be designed in such a way, that they donít disturb maximally parallel operation of the units, and that the CPU as a whole works in the same manner as in a standard PLC. The paper presents hardware solutions supporting effective operation of PLC CPU-s. Possibilities of solving problems concerning data exchange between a CPU and peripheral circuits were presented, with a special stress on timers and counters, and also on data exchange between the bit unit and the byte unit. The objective of the proposed solutions is to decrease the time necessary for a CPU to access its peripheries.
  
Key words: 

Programmable Logic Controller, Bit-Byte Structure of CPU, Control Program, Scan Time, Response Time, Throughput Time, Timer Function, Counter Function, Concurrent Operation.


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Copyright ® Bulletin of the Polish Academy of Sciences: Technical Sciences

October 2008